1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to a process for forming a self-aligned polysilicon contact, with a reduced aspect ratio contact opening, reduced chance of keyhole problems, and reduced chance of contact to bit line shorting.
2) Description of the Prior Art
The use of self aligned contact (SAC) processes has resulted in higher performance, lower cost, and increased density in semiconductor devices. If a self-aligned contact process, spacers are formed on the sidewalls of conductive structures (such as gates or bit lines). A dielectric layer is formed over these conductive structures. A contact opening is etched through the dielectric layer. A conductive layer, such as for capacitor crowns, is formed over the conductive structures and in the contact opening. However, as device dimensions and die sizes continue to decrease for higher density, the gap between adjacent conductive structures becomes narrower. Sidewall spacers make the gap even narrow, resulting in a high aspect ratio for photolithography which reduces accuracy.
Another problem is caused by an overhang of the dielectric layer. As the gap width decreases the overhang of the dielectric layer can close the gap at the top before the gap is completely filled resulting in a void (or key hole) in the dielectric layer. The key hole can fill with conductive material during subsequent formation of a conductive contact layer causing two separate devices (such as capacitors) which are formed over the dielectric layer to short. The short can result in cell failure.
Yet another problem which can occur in a self aligned contact process is silicon nitride etch through. The dielectric layer must be completely removed from above the contact plug in order to achieve a low contact resistance. Over-etching can cause etch through of the hard mask and/or the sidewall spacer and an electrical short between the conductive structure and the adjacent self aligned contact.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,565,372 (Kim) shows a SAC process comprising: forming a blanket dielectric layer, a conductive layer, and another dielectric layer over a gate with a hard mask; etching through the dielectric layer and conductive layer to form a contact opening; and forming a dielectric spacer on the sidewalls of the contact opening.
U.S. Pat. No. 5,547,893 (Sung) shows an oxide spacer if a self-aligned bit line contact.
U.S. Pat. No. 5,252,352 (Woo et al.) shows spacers on contact holes.
U.S. Pat. No. 5,795,827 (Liaw et al.) shows a SAC.